CV

Education

• M.S. in Integrated Circuit Engineering, Southeast University, 2029 (expected)
• B.E. in Microelectronics Science and Engineering, Lanzhou University, 2024

Research experience

• Design of Intelligent Acquisition System Based on FPGA
  • Undergraduate Thesis Project, Nov. 2025 – May. 2026
  • Designed an FPGA based voltage acquisition system, achieving electrical signal acquisition, frequency domain computation, and host computer display.
  • Implemented digital logic circuit modules in Verilog, covering dual channel ADC driving, signal filtering, RAM data storage, FFT IP core invocation, and UART communication.
  • Developed a host computer display module in Python to receive time domain and frequency domain data, calculate signal frequency and amplitude in real time, and dynamically plot graphs using matplotlib.
  • Tested the system using ModelSim, SignalTap II, and a signal generator; obtained frequency measurement error ≤ 3% and amplitude measurement error ≤ 8%.
  • Supervisor: Tenghu Cui

Skills

• Hardware Description & Programming
  • HDL: Verilog
  • Languages: Python, C/C++
• Digital IC Design
  • Simulation: Mentor Graphics ModelSim
  • Synthesis & Timing: Synopsys Design Compiler,
• FPGA Development
  • Altera Quartus